1. Field of the Invention
The present invention generally relates to a semiconductor circuit device. More particularly, the present invention relates to an arrangement of a decoding circuit decoding an address signal of a plurality of bits.
2. Description of the Background Art
Many semiconductor devices include a circuit for selecting one of a plurality of selection-object circuits or elements in accordance with a selection signal. A typical example of such a selection circuit is an address decoding circuit producing a signal for selecting data in a specified memory location in a memory circuit in accordance with an address signal.
In a memory device, such as an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), and a nonvolatile memory, memory cells are arranged in rows and columns. A row of and a column of memory cells are selected in accordance with an address signal. For selection of memory cells, address decoding circuits are arranged corresponding to the rows and the columns. A set of address signal bits is preallocated to each of these address decoding circuits.
A decoding circuit is selected, which is arranged corresponding to an addressed row or column, and a selection signal for the corresponding row or column is activated. In such address decoding circuitry, a circuit with identical configuration is arranged repeatedly corresponding to the rows or the columns. A different combination of address signal bits is allotted to each decoding circuit. The repeated arrangement of the circuit with the same configuration simplifies a layout of the decoding circuitry. In addition, since identical pattern is repeated, the patterning can be simpler, and operational characteristics can be made the same among the circuits.
Japanese Patent Laying-Open No. 2001-189655 discloses a configuration in which, for reducing an area occupied by decoding circuitry, P and N MOS transistors (insulated gate field effect transistors) are arranged perpendicularly to word lines and the threshold voltages of the transistors are made different from other circuit components.
In order to achieve a high-speed circuit operation, a decoding operation should be performed as fast as possible. In the case of an address signal, a large number of decoding circuits are connected to an address signal line, and thus, load thereon is large. In addition, since an address signal line is commonly provided for many decoding circuits, length of interconnection lines increases. Therefore, capacitance of the address signal line is large, and address signals cannot be switched at high speed, resulting in a longer access cycle period.
Such an increase in load on a signal line is typically seen in an address signal. In another decoding circuit, which produces a selection signal or an operation mode instruction signal in accordance with a control signal, a great number of circuits are similarly connected to a single signal line. Thus, a problem arises that the load thereon is large and the signal line cannot be driven at high speed.
In the above prior art document, only reduction in area occupied by a decoder is considered, and there is no consideration concerning a load on a decoding signal.
An object of the present invention is to provide a semiconductor circuit device achieving a high-speed decoding operation.
Another object of the present invention is to provide a semiconductor circuit device with a transistor arrangement allowing reduction in load on a signal line.
A semiconductor circuit device in accordance with one aspect of the present invention includes a plurality of first interconnection lines respectively transmitting a plurality of signals, and a plurality of first transistors arranged corresponding to the plurality of first interconnection lines. Each of the first transistors is provided in a region below a corresponding first interconnection line, and has a control electrode electrically connected with the corresponding first interconnection line.
A semiconductor circuit device in accordance with another aspect of the present invention includes a plurality of first interconnection lines respectively transmitting a plurality of signals, and a plurality of first transistors arranged corresponding to the plurality of signals and producing output signals in accordance with corresponding signals. Each of the first transistors is provided below an interconnection line region different from a region of a first interconnection line transmitting a signal different from the corresponding signal.
By providing a transistor near a region of an interconnection line transmitting the corresponding signal, an interconnection line between the transistor and the corresponding signal line can be shortened, and the line capacitance can be reduced. In addition, a layout of the interconnection line between the signal line and the corresponding transistor can be simplified.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.